1. Field of the Invention
The present invention relates generally to data communication circuits, and more particularly to a circuit and method for synchronizing data communication using a set of storage banks.
2. Description of the Related Art
Modem computer systems generally include one or more memory units such as random-access-memory (RAM), read-only-memory (ROM), FIFOs, etc. The memory units store data and instructions for use by a processor, which is coupled to the memory units via a memory bus. In communicating data and instructions, data capture devices such as toggle synchronizers are routinely used to synchronize communication between two devices having different data throughput rates. These data capture devices receive data from one device at one speed and store the data into FIFOs or register files. The stored data are then transmitted to the other device at a speed optimized for the latter device.
FIG. 1 shows a block diagram of a conventional computer system 100 including a processor 102 and a chip containing a memory device 104. The chip containing the memory device 104 is coupled to the processor 102 and includes a buffer circuit 108 and a memory unit 114. The memory unit 114 may be a random access memory (RAM) in the form of an internal register file. The buffer circuit 108 receives and buffers data for synchronized data transmission between the processor 102 and the memory unit 114. To perform I/O operations, the processor 102 typically generates and transmits read/write control signals 112 (e.g., address, data, enable, etc.) to the chip with memory device 104. For example, in read operations, the memory device 104 fetches data from the memory unit 114 and stores the data in the buffer circuit 108. The requested data in the buffer circuit 108 are then transmitted to the processor 102 for processing.
In general, however, since the processor 102 can process data at a much faster rate than the memory device 104 is capable of operating, the memory device 104 often transmits a NOT_READY signal 110 to indicate that data is currently unavailable in the buffer circuit 108. In response, the processor 102 stops initiating read/write operations and may perform other tasks while the NOT_READY signal 110 is asserted. When the requested data has been fetched into the buffer circuit 108, the memory device 104 de-asserts the NOT_READY signal and provides the data to the processor 102.
Unfortunately, however, the assertion of NOT_READY signals generally degrades performance of the computer system 100 by interrupting read/write operations. This is because the processor 102 must switch from performing one task to another task and then switch back to the original interrupted task when data becomes available. Furthermore, the interruption not only delays the interrupted read/write task but also all subsequent read/write operations. This means that the processor 104 is not efficiently utilized since the memory device 104 stops further read/write operations by the processor 102 until the interrupted read/write operation is completed. Thus, the interruption in such read/write operations may cause a bottleneck limiting the performance of high-speed successive read/write operations. By way of example, disk drive controllers 104 are often called upon by the processor 102 to perform many read/write operations to or from FIFOs. In such situations, interruptions in read/write operations delay the access of disk drive controller and thus slow down the response times of computer systems in general.
In view of the foregoing, there is a need for a circuit and method that can transmit data between devices having different data throughput rates without interruption.